Hardware module (Symbolator)

Symbolator reads a VHDL or Verilog declaration and draws the block symbol. Because it reads the real interface, the picture cannot drift from the code.

#What this example shows

• Port grouping comments, which organise the symbol.

• Generics rendered as part of the interface.

• Directions placing ports on the correct side.

#A worked example

Open it, edit it, or copy the source below.

The source, which you can paste into a new diagram and edit:

component spi_master is
  generic (
    CLK_FREQ  : integer := 50_000_000;
    SPI_FREQ  : integer := 1_000_000;
    DATA_WIDTH: integer := 8
  );
  port (
    --# {{clocks|}}
    clk       : in  std_ulogic;
    rst_n     : in  std_ulogic;

    --# {{control|Control}}
    start     : in  std_ulogic;
    busy      : out std_ulogic;
    done      : out std_ulogic;

    --# {{data|Data}}
    tx_data   : in  std_ulogic_vector(DATA_WIDTH-1 downto 0);
    rx_data   : out std_ulogic_vector(DATA_WIDTH-1 downto 0);

    --# {{spi|SPI bus}}
    sclk      : out std_ulogic;
    mosi      : out std_ulogic;
    miso      : in  std_ulogic;
    cs_n      : out std_ulogic
  );
end component;

#Making it your own

• Only the declaration is read, so paste the header rather than the whole file.

• The group comments are what make a wide interface readable.

• Regenerate rather than editing the picture; that is the entire point.

#Related

Specialists. Borrow one when you need it.