Symbolator

Symbolator reads VHDL or Verilog component or module declarations and draws the block symbol, with ports grouped and placed by direction.

Because it reads the real declaration, the symbol cannot drift from the interface.

#What it is good at

• Hardware module interface documentation.

• Design reviews where the port list is the subject.

• Integration diagrams assembled from generated symbols.

#What it draws

#A worked example

A Verilog module, drawn as a symbol:

The source, which you can paste into a new diagram and edit:

module spi_master #(
  parameter CLK_DIV = 4,
  parameter WIDTH  = 8
) (
  //# {{clocks|}}
  input  wire clk,
  input  wire rst_n,
  //# {{control|Control}}
  input  wire start,
  output wire busy,
  output wire done,
  //# {{data|Data}}
  input  wire [WIDTH-1:0] tx_data,
  output wire [WIDTH-1:0] rx_data,
  //# {{spi|SPI bus}}
  output wire sclk,
  output wire mosi,
  input  wire miso,
  output wire cs_n
);
endmodule

#A few things that catch people out

• Only the declaration is read; the body is ignored, so paste the header rather than the file.

• The group comments are what make a wide interface readable. Use them.

• Regenerate rather than editing the picture; that is the whole reason to use it.

#Related

Thirty-one languages. Nobody knows them all.