# HDL block diagram Symbolator reads VHDL or Verilog component declarations and draws the block symbol: ports on the correct sides, buses grouped, names exactly as declared. Generating it means the documentation cannot drift from the interface, which is the usual failure of hand-drawn block symbols. --- ## When to reach for one * Documenting module interfaces in a hardware design. * Integration diagrams showing how modules connect. * Design reviews where the port list is the subject. --- ## How to draw it in Capable | **Route** | **Use when** | | ---------- | ------------------------------------------------------- | | Symbolator | Generated directly from HDL source; never out of date. | | draw.io | System-level diagrams built from the generated symbols. | --- ## A worked example A component declaration, drawn as a block symbol: ![HDL block diagram](https://help.gocapable.com/images/att1433960455.svg) The source, which you can paste into a new diagram and edit: ``` component uart_rx is generic ( CLK_FREQ : integer := 50_000_000; BAUD_RATE : integer := 115_200 ); port ( --# {{clocks|}} clk : in std_ulogic; rst_n : in std_ulogic; --# {{data|Serial}} rx : in std_ulogic; --# {{|Parallel}} data : out std_ulogic_vector(7 downto 0); data_valid: out std_ulogic; frame_err : out std_ulogic ); end component; ``` --- ## A few things that catch people out * Keep the source as the single definition; regenerate the diagram rather than editing it. * Section comments group ports on the symbol, which is what makes a large interface readable. * Generics belong on the symbol. They are part of the interface. --- ## Related [Memory layout diagramOffsets, widths and nested structures.](https://help.gocapable.com/diagrams/memory-layout-diagram.html) [Neural network diagramLayers, connections and shapes.](https://help.gocapable.com/diagrams/neural-network-diagram.html) [ExamplesWorking diagrams you can copy.](https://help.gocapable.com/diagrams/examples.html) --- _Approximately right is wrong here._